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White Paper
High Speed ADC Data Transfer

By Scott Lewis
City Semiconductor, Inc.

Introduction

When continuously running a high speed ADC, it can be a challenge to deal with the firehose of raw data available at the output.  To use City Semiconductor’s 2.5 GS/s 12-bit ADC, for example, 30 gigabits per second of data have to be accepted.

The main architectural choice for this problem is whether to process the data on chip or to send it immediately off chip.  Both of these options have design implications that need to be considered from the start.  In order to get the data off-chip using a reasonable amount of pins, a serializer (SERDES) or LVDS interface must be designed, along with all of the peripheral circuits that it requires.  Using the data on chip doesn’t have the limitation for the number of pins, but care must be taken in order to ensure a clean hand-off between clock and supply domains.

On-Chip Data

City Semiconductor’s IP allows the high speed ADC to be placed on the same chip as other functional blocks and circumvent the need for SERDES, allowing significant design cost savings. There are still several problems that need to be solved, but can be approached with conventional circuits that don’t have long design times.

Timing Considerations

One such problem is that in time interleaved designs, there are many groups of data outputs that update sequentially.  In order to utilize a single data clock, a multi-stage retiming strategy is needed.  The general idea is that the interleaved phase clocks can be reused to latch data from other phases during a time that those data are held stable, ensuring maximum setup and hold time.  Data is then presented to the output all at once on a single clock phase.

An example of this idea is a 32-way interleaved design.  The timing details are shown in figure 1.  The clock generator outputs 32 clock phases for each slice that are each separated by 1 high speed clock period.  The raw data for each of the slices updates one at a time on the rising edges of these clocks.  If a single retiming phase was used, there would be one slice with the hardest timing requirements, and every other sl ic e wo ul d be easy.  In order to ease th e ha rd es t requirements, the data is retimed in groups.  Slices 0-15 can be retimed with phase 23, and slices 16-31 can be retimed with phase 7.  These two groups can be retimed again with a phase between them so that all the data updates on the same clock.  This strategy ensures that the data is not changing for several phases around the retiming clock and special treatment is not required.  The main cost for this extra margin is latency.

Figure 1. Timing Details for Data Output
Figure 1. Timing Details for Data Output

Crossing Supply Domains

Once the retiming strategy is used, there are now many latches all firing at the same time. The data outputs can travel long distances across the chip and have high capacitive loads and need large drivers. As a consequence of this, there will be a big transient current spike on the supply voltage connected to these latches and drivers. Usually a clean analog supply is used throughout the ADC array, but a core digital supply should be used here in order to prevent any fixed frequency IR drop from corrupting the analog signal. Routing the digital supply into the core ADC area should be safe as long as there are no overlapping current paths between the domains.

Crossing Clock Domains

Another timing requirement is that the ADC should be able to present stable data for an external digital block to capture it with its own clock with unknown phase alignment with the ADC or data clock.  This problem can be circumvented by using the ADC clock to drive the digital section, but in case this is not possible then extra circuitry needs to be added to ensure a clean handoff.  A simple way to achieve this is to build a FIFO.  A high word depth is not required as long as it is known that the digital system will take the data as fast as it is generated in normal operation.  The main tradeoff for this approach is extra gate count because at least 3 flip-flops and a multiplexer are needed for every bit, but in fine processes this is not a huge area overhead.

Figure 2 shows an example 3-word FIFO with 2 separate clocks for reading and writing.  As long as the counters are reset to different values, then the data will never be read at the same time that it is changing. A clock gate circuit (CG) is attached to each FIFO stage so that only one stage is changing at a time.

Figure 2. 3-word FIFO
Figure 2. 3-word FIFO

Off-Chip Data

One way to get the data off chip is to simply translate it to LVDS and send it out in parallel.  This method does not require any training patterns or accurate clock phase generation, but may require too many pins depending on the application.

To drive data off-chip at a reasonable speed without using too many pins, a serializer must be used. The SERDES alone adds significant complexity to the design, but even if SERDES IP is already on-hand, it must be connected to the ADC properly.


Figure 3 shows a possible block diagram of the overall ADC IP using a SERDES to drive off chip.  In this example, each SERDES lane uses a baud rate based on the ADC clock, so a  PL L is not required.  The embedded clock generator does still have to generate this clock and meet all timing requirements to ensure internal data fidelity.

If the ADC clock cannot be used for the SERDES, a clock handoff block needs to be implemented similar to the way it needs to be handled for crossing clock domains on-chip. Even if the ADC clock is used, care must still be taken to ensure the SERDES divider powers up in a known state. One way to do this is to send a synchronization signal based on the clk gen divider that resets the SERDES divider so that the two dividers are always in a relative alignment.

Figure 3. Block Diagram of ADC with SERDES Driver
Figure 3. Block Diagram of ADC with SERDES Driver

Conclusion

There are many intricacies with using the high speed data stream coming from a gigasample ADC, and some of them were covered here.  How a design solves this problem can dr iv e  ma jo r architecture choices such as utilizing the data on-chip vs. of f- ch ip  an d  sh ou ld  be considered very early on in the definition phase.  The main things to consider are circuitry overhead, design difficulty, and latency.  A good design will trade off these factors to best fit each unique set of requirements.

About City Semiconductor, Inc.

City Semiconductor is a mixed-signal IC design house providing world-class intellectual property for the highest-speed applications, specializing in data converters (ADC’s and DAC’s) that operate in the Gigahertz range.  City Semiconductor also provides custom and semi-custom design and layout services, and turnkey prototyping services.  Their quickly-growing portfolio includes proven designs implemented in nodes ranging from 14nm to 180nm, at popular foundries worldwide.

City Semiconductor is located in San Francisco, California, and can be found at www.citysemi.com

Or visit the Design & Reuse partner page  (www.design-reuse.com/sip/supplier/1111/city-semiconductor)




White Paper
Interleaved ADC Calibration Techniques

By Chris Menkus and Scott Lewis
City Semiconductor, Inc.

Overview

Commercial time-interleaved ADCs have been available since the early 2000’s.  Since then the number of academic and industry-sponsored articles showing the advantages of interleaving has been steadily increasing. 

Interleaving provides clear advantages in terms of power and speed.  This is mainly due to the square-law dependence between current and bandwidth in analog signal paths, and secondly because we can take better advantage of clever architectural innovations with lower-speed circuits.

Figure 1. Basic block diagram of an interleaved ADC
Figure 1. Basic block diagram of an interleaved ADC

The main challenge of interleaving, of which most people are now aware, is that un-treated mismatch between interleaved units can cause spurs in the output spectrum. The source of this mismatch is usually random variation in the semiconductor processing, and is unavoidable for mid-to-high resolution ADCs. Gain and offset mismatch may be considered as DC effects, while the effects of timing and bandwidth mismatch become worse with higher-frequency analog inputs.

Figure 2. An example gain mismatch waveform and the resulting output spectrum
Figure 2. An example gain mismatch waveform and the resulting output spectrum


Various forms of calibration have been proposed to correct these mismatches and reduce the resulting spurs. Gain and offset mismatch correction are the most straightforward, and will be discussed first. A calibration routine may be considered as “foreground” or “background”, depending on whether or not the output data stream is interrupted during processing.

Foreground Calibration

Foreground calibration implies that the converter is taken off-line for a short period of time in order to inject some form of reference signal, or to force circuit blocks into a known state. With the reference applied, the converter output is sensed in order to determine the direction and amount of correction needed. Correction may either be applied through an analog feedback DAC, or as a digital post-processing step. This form of calibration may be considered the most generic, because it does not require a specific type of input signal.

Figure 3. An example of a foreground calibration period
Figure 3. An example of a foreground calibration period


The injected reference signal may be static, for example 0V differential (ie. shorted inputs) to measure differential offsets, or stepped through a range of values to stimulate multiple codes.  If desired, the unit quantizer’s linearity may also be measured and improved with a stepped range of input values, but this is another separate topic.

Foreground calibration is useful for applications where the input signal is not known ahead of time or may behave in unpredictable ways. 

The drawbacks of foreground calibration include the requirement to tolerate a temporary loss of data while the calibration routine runs.  Some applications may be better suited to tolerate this.  For example, a transceiver that sends and receives signals on the same I/O pin at different times can calibrate the ADC during the transmit phase.  Test & measurement and range finding (eg. LIDAR) equipment are other examples of systems where data is sporadic and there may be a natural down-time for performing repeated calibrations.

Background Calibration

As the name implies, background calibration works in the “background” to sense and correct various sources of mismatch. Its main advantage is that normal output data is not interrupted. Background calibration compensates for drifts due to time, temperature, or supply variation, but puts extra requirements on the input signal. The input must either obey a known statistical behavior, or if it doesn’t, a calibration tone or dithering signal must be added to the signal path and then subtracted out at a later stage.

Figure 4. An example of an interleaved ADC with background calibration
Figure 4. An example of an interleaved ADC with background calibration


The simplest form of background calibration is to rely on the statistical properties of the input signal to exercise the individual interleaved units in a similar-enough way to allow relative comparisons.  The unit outputs are then averaged, compared, and their errors extracted.  As a simple example, if the analog input is a beat frequency of the sample clock, each unit ADC will eventually sample the same set of points along the sinewave, and should theoretically produce the same set of digital output codes.  Any deviation from the average produces a corrective feedback from the calibration engine.

Another form of background calibration relies on one or more redundant units being included in the array, such that one or more may be taken offline for correction, while the redundant unit takes its place.  The unit under test may be driven to a known state and compared to a reference.  Each unit may be taken off-line and measured one-at-a-time, so that the entire array will eventually match.

The backend circuitry which calculates the mismatch and the required adjustments may either be left free-running, or disabled and enabled periodically to save power and reduce noise, depending on the input data or the desired update time constant.  All background calibration techniques rely on a slow convergence towards a desired state over multiple iterations.

With all types of calibration the digital circuitry benefits greatly from technology scaling.  Its area and power overhead make up only a small percentage of the overall chip in modern deep submicron processes.

Timing Mismatch

Sample clock timing mismatch is a special case which may not be as easily corrected with the calibration techniques described above. Its effects are worse for single-tone full-scale sinewave inputs, for which a small change in sampling instant may result in large voltage errors. Luckily such full-scale sinewaves are not common in modulated or broadband communications systems.

Figure 5. An example timing mismatch waveform and the resulting output spectrum
Figure 5. An example timing mismatch waveform and the resulting output spectrum

As an alternative to calibration we can effectively eliminate timing mismatch with a multi-rank Track & Hold (T&H) that utilizes a single sampling circuit operating at the highest frequency, fs.  Once the high speed signal is sampled, it is then distributed to multiple lower-speed samplers and quantizers.  In this way timing skews between interleaved units are less critical.  This is the approach taken with City Semiconductor’s current Gigasample-per-second (GS/s) family of ADCs.

In the below example diagram, only the clock going to the “TH” block is critical.  All other clocks are not as critical because they are sampling a signal that is held constant.  Additionally, each individual ADC unit only needs to convert at 1/N of the full sampling rate.

Figure 6. An example of an interleaved ADC with single up-front T&H
Figure 6. An example of an interleaved ADC with single up-front T&H


This approach is quite effective with a good CMOS process and clock speeds up to 3 GHz.  As we move to higher sampling rates a single T&H will suffer from various dynamic effects, and the loading from multiple interleaved quantizers will become prohibitive.  At that point the input T&H must also be interleaved, and static timing mismatch corrected by some form of calibration.

One option to calibrate for static timing mismatch is to use an iterative “detect and adjust” approach that senses the voltage errors on a known reference signal caused by timing mismatch, and adjusts a delay line to offset one T&H’s sampling instant with respect to the others until the error is reduced to an acceptable level.  The challenge, of course, is injecting this reference signal and measuring it in a repeatable way.

Figure 7. An example of an interleaved ADC with timing calibration
Figure 7. An example of an interleaved ADC with timing calibration


Another option is to use digital post-processing and a mathematical model based on taking the discrete time derivative to estimate the error based on live data.  Several recent conference and journal articles describe such a technique.  The cost of this approach is increased digital complexity, and perhaps a reduced usable input frequency range.

Note that bandwidth mismatch is a less common effect which can usually be accounted for with good layout practices, so we won’t discuss it here separately.  The spur it creates in the output spectrum is in the same location as the spur caused by timing mismatch.

Putting It All Together

The latest 2.5-GSPS ADC family from City Semiconductor includes circuitry for both foreground and background calibration, to provide the most flexible solution for a wide variety of applications.  All reference circuitry is provided on-chip.

While we don’t expect more than one form of calibration would be needed for a single application, when working with IP it is important to be able to quickly port the design from one application to the next, in a variety of process nodes.  It is also important to understand the various causes and effects of mismatch in interleaved data converter arrays, and choose the right type of calibration for the target application.


About City Semiconductor, Inc.

City Semiconductor is a mixed-signal IC design house providing world-class intellectual property for the highest-speed applications, specializing in data converters (ADC’s and DAC’s) that operate in the Gigahertz range.  City Semiconductor also provides custom and semi-custom design and layout services, and turnkey prototyping services.  Their quickly-growing portfolio includes proven designs implemented in nodes ranging from 14nm to 180nm, at popular foundries worldwide.

City Semiconductor is located in San Francisco, California, and can be found at www.citysemi.com

Or visit the Design & Reuse partner page  (www.design-reuse.com/sip/supplier/1111/city-semiconductor)




City Semiconductor Announces Leading-Edge 12-bit 2.5-GSPS SAR ADC IP in 40nm

SAN FRANCISCO – January 25, 2015 – City Semiconductor, a proven supplier of leading-edge mixed signal IP and related design services and support, announces an interleaved SAR (Successive Approximation Register)  ADC with 12 bits of resolution at conversion rate of up to 2.5-GSPS (Gigasamples per second). Implemented in a popular 40nm process, this IP provides an industry-leading combination of high speed, low power consumption and flexibility for software defined  radio,  wireless networking, satellite communications, radar, and high-performance Test & Measurement equipment.

The third-generation CS_AD122500_UMC40LP design provides exceptional noise performance while consuming significantly less power compared to existing solutions. Foreground calibration can be implemented on demand, which incurs a brief interruption in the output data flow. And, in order to meet the needs of communications applications which cannot tolerate interruptions in service the design also offers background calibration, which is totally invisible to the user.  To simplify the design-in, City provides all needed voltage references and clock phase generation circuitry onboard. Also, the converter is easily configured as either a single, or a dual, for quadrature demodulation. Although currently implemented in the UMC 40nm process, the design is easily ported to other popular foundries.

About City Semiconductor, Inc.

City Semiconductor is a mixed-signal IC design house providing world-class intellectual property for the highest-speed applications, specializing in data converters (ADC’s and DAC’s) that operate in the Gigahertz range.  City Semiconductor also provides custom and semi-custom design and layout services, and turnkey prototyping services.  Their quickly-growing portfolio includes proven designs implemented in nodes ranging from 14nm to 180nm, at popular foundries worldwide.

City Semiconductor is located in San Francisco, California, and can be found at www.citysemi.com

Or visit the Design & Reuse partner page  (www.design-reuse.com/sip/supplier/1111/city-semiconductor)