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Data I/O

Configuration

6 Gbps Serializer PHY with Loopback
Parrallel LVDS Output Interface

Process Node(s)

65nm, 40nm
180nm, 65nm, 40nm

 

Clocking

Configuration

200 MHz to 2.5 GHz Clock Receiver
 200 MHz to 2.5 GHz DLL

Process Node(s)

180nm, 65nm, 40nm
 180nm, 65nm, 40nm

 

Misc. Analog

Configuration

Bandgap Voltage Reference
Bias Current Generation & Distribution
Power-On Reset

Process Node(s)

 180 nm, 65nm, 40nm, 14nm FF
 180 nm, 65nm, 40nm, 14nm FF
 180nm, 65nm, 40nm